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4–4
Chapter 4: Development Board Setup
Factory Default Switch Settings
Table 4–1. SW1 Dip Switch Settings (Part 2 of 2)
Switch
Board
Label
Function
Default
Position
Switch 3 has the following options:
3
CLK100_EN
■
When on, the 100 MHz clock is disabled.
Off
■
When off, the 100 MHz clock is enabled.
Switch 4 has the following options:
4
CLK125_EN
■
When on, the 125 MHz clock is disabled.
Off
■
When off, the 125 MHz clock is enabled.
3. Set DIP switch bank (SW2) to match Table 4–2 and Figure 4–1 .
Table 4–2. SW2 Dip Switch Settings
Switch
Board
Label
Function
Default
Position
Switch 1 is a MAX II user-defined switch and has the following options:
1
DIP0
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 2 is a MAX II user-defined switch and has the following options:
2
DIP1
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 3 is a MAX II user-defined switch and has the following options:
3
DIP2
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 4 is a MAX II user-defined switch and has the following options:
4
DIP3
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 5 is a MAX II user-defined switch and has the following options:
5
DIP4
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 6 is a MAX II user-defined switch and has the following options:
6
DIP5
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 7 is a MAX II user-defined switch and has the following options:
7
DIP6
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 8 has the following options:
8
CLK66_SEL
■
When closed, the 66 MHz clock is selected.
Closed
■
When open, the SMA input clock is selected.
Stratix IV E FPGA Development Kit User Guide
June 2011 Altera Corporation
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